With each successive semiconductor technology generation, wafer diameters tend to increase and transistor sizes decrease, resulting in the need for an ever higher degree of accuracy and repeatability in substrate processing. Semiconductor substrate materials, such as silicon wafers, are routinely processed using plasma processing chambers. Plasma processing techniques include sputter deposition, plasma-enhanced chemical vapor deposition (PECVD), resist strip, and plasma etch. Plasma can be generated by subjecting suitable process gases in a plasma processing chamber to radio frequency (RF) power. Flow of RF current in the plasma processing chamber can affect the processing.
A plasma processing chamber can rely on a variety of mechanisms to generate plasma, such as inductive coupling (transformer coupling), helicon, electron cyclotron resonance, capacitive coupling (parallel plate). For instance, high density plasma can be produced in a transformer coupled plasma (TCP™) processing chamber, or in an electron cyclotron resonance (ECR) processing chamber. Transformer coupled plasma processing chambers, wherein RF energy is inductively coupled into the chambers, are available from Lam Research Corporation, Fremont, Calif. An example of a high-flow plasma processing chamber that can provide high density plasma is disclosed in commonly-owned U.S. Pat. No. 5,948,704, the disclosure of which is hereby incorporated by reference. Parallel plate plasma processing chambers, electron-cyclotron resonance (ECR) plasma processing chambers, and transformer coupled plasma (TCP™) processing chambers are disclosed in commonly-owned U.S. Pat. Nos. 4,340,462; 4,948,458; 5,200,232 and 5,820,723, the disclosures of which are hereby incorporated by reference.
By way of example, plasma can be produced in a parallel plate processing chamber such as the dual frequency plasma etching chamber described in commonly-owned U.S. Pat. No. 6,090,304, the disclosure of which is hereby incorporated by reference. A preferred parallel plate plasma processing chamber is a dual frequency capacitively coupled plasma processing chamber including an upper showerhead electrode and a substrate support. For purposes of illustration, embodiments herein are described with reference to a parallel plate type plasma processing chamber.
A parallel plate plasma processing chamber for plasma etching is illustrated in FIG. 1. The plasma processing chamber 100 comprises a chamber 110, an inlet load lock 112, and an optional outlet load lock 114, further details of which are described in commonly-owned U.S. Pat. No. 6,824,627, which is hereby incorporated by reference in its entirety.
The load locks 112 and 114 (if provided) include transfer devices to transfer substrates such as wafers from a wafer supply 162, through the chamber 110, and out to a wafer receptacle 164. A load lock pump 176 can provide a desired vacuum pressure in the load locks 112 and 114.
A vacuum pump 172 such as a turbo pump is adapted to maintain a desired pressure in the chamber 110. During plasma etching, the chamber pressure is controlled, and preferably maintained at a level sufficient to sustain a plasma. Too high a chamber pressure can disadvantageously contribute to etch stop while too low a chamber pressure can lead to plasma extinguishment. In a medium density plasma processing chamber, such as a parallel plate plasma processing chamber, preferably the chamber pressure is maintained at a pressure below about 200 mTorr (e.g., less than 100 mTorr such as 20 to 50 mTorr) (“about” as used herein means ±10%).
The vacuum pump 172 can be connected to an outlet in a wall of the chamber 110 and can be throttled by a valve 173 in order to control the pressure in the chamber. Preferably, the vacuum pump is capable of maintaining a pressure within the chamber 110 of less than 200 mTorr while etching gases are flowed into the chamber 110.
The chamber 110 includes an upper electrode assembly 120 including an upper electrode 125 (e.g., showerhead electrode), and a substrate support 150. The upper electrode assembly 120 is mounted in an upper housing 130. The upper housing 130 can be moved vertically by a mechanism 132 to adjust the gap between the upper electrode 125 and the substrate support 150.
A process gas source 170 can be connected to the housing 130 to deliver process gas comprising one or more gases to the upper electrode assembly 120. In a preferred plasma processing chamber, the upper electrode assembly comprises a gas distribution system, which can be used to deliver process gas to a region proximate to the surface of a substrate. Gas distribution systems, which can comprise one or more gas rings, injectors and/or showerheads (e.g., showerhead electrodes), are disclosed in commonly-owned U.S. Pat. Nos. 6,333,272; 6,230,651; 6,013,155 and 5,824,605, the disclosures of which are hereby incorporated by reference.
The upper electrode 125 preferably comprises a showerhead electrode, which includes gas holes (not shown) to distribute process gas therethrough. The gas holes can have a diameter of 0.02 to 0.2 inch. The showerhead electrode can comprise one or more vertically spaced-apart baffle plates that can promote the desired distribution of process gas. The upper electrode and the substrate support may be formed of any suitable material such as graphite, silicon, silicon carbide, aluminum (e.g., anodized aluminum), or combinations thereof. A heat transfer liquid source 174 can be connected to the upper electrode assembly 120 and another heat transfer liquid source can be connected to the substrate support 150.
The substrate support 150 can have one or more embedded clamping electrodes for electrostatically clamping a substrate on an upper surface 155 (support surface) of the substrate support 150. The substrate support 150 can be powered by an RF source and attendant circuitry (not shown) such as RF matching circuitry. The substrate support 150 is preferably temperature controlled and may optionally include a heating arrangement (not shown). Examples of heating arrangements are disclosed in commonly assigned U.S. Pat. Nos. 6,847,014 and 7,161,121, which are hereby incorporated by reference. The substrate support 150 can support a semiconductor substrate such as a flat panel or 200 mm or 300 mm wafer on the support surface 155.
The substrate support 150 preferably includes passages therein for supplying a heat transfer gas such as helium under the substrate supported on the support surface 155 to control the substrate temperature during plasma processing thereof. For example, helium back cooling can maintain wafer temperature low enough to prevent burning of photoresist on the substrate. A method of controlling a temperature of a substrate by introducing a pressurized gas into a space between the substrate and the substrate support surface is disclosed in commonly-owned U.S. Pat. No. 6,140,612, the disclosure of which is hereby incorporated by reference.
The substrate support 150 can include lift pin holes (not shown), through which lift pins can be actuated vertically by suitable mechanisms and raise the substrate off the support surface 155 for transport into and out from the chamber 110. The lift pin holes can have a diameter of about 0.08 inch. Details of lift pin holes are disclosed in commonly owned U.S. Pat. Nos. 5,885,423 and 5,796,066, the disclosures of which is hereby incorporated by reference.
FIG. 2 shows a block diagram of a capacitively coupled plasma processing chamber 200 to illustrate flow path of RF current therein. A substrate 206 is being processed within processing chamber 200. To ignite the plasma for etching substrate 206, a process gas in the chamber 200 is subjected to RF power. RF current may flow from an RF supply 222 along a cable 224 through an RF match network 220 into processing chamber 200 during substrate processing. The RF current may travel along a path 240 to couple with the process gas to create plasma within a confined chamber volume 210 for processing substrate 206, which is positioned above a bottom electrode 204.
In order to control plasma formation and to protect the processing chamber walls, a confinement ring 212 may be employed. Details of an exemplary confinement ring are described in commonly owned U.S. Provisional Patent Application Ser. Nos. 61/238,656, 61/238,665, 61/238,670, all filed on Aug. 31, 2009, and U.S. Patent Application Publication No. 2008/0149596, the disclosures of which are hereby incorporated by reference. The confinement ring 212 may be made of a conductive material such as silicon, polysilicon, silicon carbide, boron carbide, ceramic, aluminum, and the like. Usually, the confinement ring 212 may be configured to surround the periphery of confined chamber volume 210 in which a plasma is to form. In addition to the confinement ring 212, the periphery of confined chamber volume 210 may also be defined by upper electrode 202, bottom electrode 204, one or more insulator rings such as 216 and 218, an edge ring 214 and a lower electrode support structure 228.
In order to exhaust neutral gas species from the confinement region (confined chamber volume 210), the confinement rings 212 may include a plurality of slots (such as slots 226a, 226b, and 226c). The neutral gas species may be pumped out of processing chamber 200 via a turbo pump 234.